Semiconductor structure and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPING-CHUNG LIU, WEI-CHIANG HUNG, HSIANG-YU TSAI, KUO HUI CHANG
Life of this patent
Estimating the term…
Abstract
A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; and a stress memorization technology (SMT) sidewall spacer over a sidewall of the gate stack. The gate stack includes a gate dielectric layer over the semiconductor substrate and a gate electrode over the gate dielectric layer. The SMT sidewall spacer provides a stress for a channel region beneath the gate stack.
Claims30
(canceled)
(canceled)
(canceled)
(canceled)
(canceled)
(canceled)
A method for manufacturing a semiconductor structure, comprising:
- forming a gate stack over a semiconductor substrate and a source/drain region adjacent to the gate stack;
- forming a capping layer over the gate stack and the semiconductor substrate;
- implanting ions on the capping layer;
- annealing the capping layer and the semiconductor substrate so as to recrystallize and deform a gate electrode of the gate stack, wherein the deformed gate electrode transfers the stress into a channel region beneath the gate stack;
- and
- removing a portion of the capping layer, thereby forming a sidewall spacer around the gate stack.
(canceled)
(canceled)
(canceled)
(canceled)
(canceled)
A method for manufacturing a semiconductor structure, comprising:
- forming a gate stack over a semiconductor substrate and a source/drain region adjacent to the gate stack;
- forming an oxide layer over the semiconductor substrate;
- forming a capping layer over the gate stack and the semiconductor substrate;
- implanting ions on the capping layer;
- annealing the capping layer and the semiconductor substrate so as to recrystallize and deform a gate electrode of the gate stack, wherein the deformed gate electrode transfers the stress into a channel region beneath the gate stack;
- and
- removing a portion of the capping layer, thereby forming a sidewall spacer around the gate stack;
- wherein the oxide layer is formed prior to the capping layer.
A method for manufacturing a semiconductor structure, comprising:
- forming a gate stack over a semiconductor substrate and a source/drain region adjacent to the gate stack;
- forming a capping layer over the gate stack and the semiconductor substrate;
- implanting ions on the capping layer;
- annealing the capping layer and the semiconductor substrate;
- etching a portion of the capping layer to form a sidewall spacer around the gate stack, wherein the sidewall spacer includes a lattice constant different from that of a gate electrode of the gate stack or the source/drain region;
- forming a metal layer over the gate stack and the source/drain region;
- and
- annealing the metal layer so as to partially silicide the gate stack and the source/drain region.
Dependencies are inferred from the claim text.