US 2016/0079416 A1Published application

Semiconductor device

AssigneeKabushiki Kaisha Toshiba

InventorsKoichi Sato, Kenya Kobayashi

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Abstract

According to an embodiment, a semiconductor device includes first semiconductor layers and a second semiconductor layer disposed between adjacent first semiconductor layers. The first semiconductor layers have first end surfaces, and the second semiconductor layer has a second end surface between the adjacent first semiconductor layers. The device includes a first electrode facing each first end surface of the adjacent first semiconductor layers via an insulating film, a second electrode in contact with side surfaces of the adjacent first semiconductor layers and the second end surface, a first semiconductor region between the second electrode and the adjacent first semiconductor layers, and a second semiconductor region in the first semiconductor region between the second electrode and each of the adjacent first semiconductor layers. The first semiconductor region and the second semiconductor region face the first electrode via the insulating film, and electrically connected to the second electrode.

Claims16

Dependent claims

A semiconductor device comprising:

an underlying layer;
first semiconductor layers of a first conductivity type arranged in a first direction perpendicular to the underlying layer, the first semiconductor layers having first end surfaces;
a second semiconductor layer of a second conductivity type disposed between the adjacent first semiconductor layers, the second semiconductor layer having a second end surface between the adjacent first semiconductor layers;
a first electrode facing each first end surface of the adjacent first semiconductor layers via an insulating film;
a second electrode in contact with each side surface of the adjacent first semiconductor layers and the second end surface;
a first semiconductor region of the second conductivity type between the second electrode and each of the adjacent first semiconductor layers, the first semiconductor region facing the first electrode via the insulating film;
and
a second semiconductor region of the first conductivity type in the first semiconductor region between the second electrode and each of the adjacent first semiconductor layers, the second semiconductor region facing the first electrode via the insulating film, and electrically connected to the second electrode.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/635,922Filed 2 Mar 2015
Priority: JP 2014-18789316 Sep 2014
Published: 17 Mar 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 62/111
Reduced surface field [RESURF] PN junction structures: multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
H10D 30/0295
Of vertical dmos [vdmos] fets: using recessing of the source electrodes
H10D 30/663
Vertical dmos [vdmos] fets: having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS
H10D 62/158
Drain regions of DMOS transistors: dispositions