A junction-modulated tunneling field effect transistor and a fabrication method thereof
AssigneePeking University
InventorsRu Huang, Qianqian Huang, Chunlei Wu, Jiaxin Wang, Zhan Zhan, Yangyuan Wang
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AssigneePeking University
InventorsRu Huang, Qianqian Huang, Chunlei Wu, Jiaxin Wang, Zhan Zhan, Yangyuan Wang
Estimating the term…
The present invention discloses a junction-modulated tunneling field effect transistor and a fabrication method thereof, belonging to a field of field effect transistor logic device and the circuit in connection with CMOS ultra large scale integrated circuit (ULSI). The PN junction provided by a highly-doped source region surrounding three sides of the vertical channel region of the tunneling field effect transistor can deplete effectively the channel region, so that the energy band of the surface channel under the gate is lifted, therefore the device may obtain a steeper energy band and a narrower tunneling barrier width than the conventional TFET when the band-to-band tunneling occurs, equivalently achieving the effect of a steep doping concentration gradient at the source tunneling junction, and thereby the sub-threshold characteristics are significantly improved while the turn-on current of the device is improved relative to the conventional TFET. Under the conditions that the device of the present invention is compatible with the existing CMOS process, on the one hand an ambipolar effect of the device can be inhibited effectively, while a parasitic tunneling current at a source junction corner in the small size device can be inhibited and thus can equivalently achieve an effect of a steep doping concentration gradient at the source junction.
A tunneling field effect transistor, comprising a semiconductor substrate (1), a vertical channel region (2), a highly-doped source region (4), a lowly-doped drain region (8), a gate dielectric layer (5), and a control gate (6), and a gate electrode (9) coupled to the control gate (6), a source electrode (10) coupled to the highly-doped source region (4), and a drain electrode (11) coupled to the lowly-doped drain region (8), wherein the vertical channel region (2) is on the semiconductor substrate (1) and has shape of cuboid;
Dependencies are inferred from the claim text.