US 2016/0079397 A1 · PARTIAL FIN ON OXIDE FOR IMPROVED ELECTRICAL ISOLATION OF RAISED ACTIVE REGIONS

Abstract

A semiconductor fin suspended above a top surface of a semiconductor layer and supported by a gate structure is formed. An insulator layer is formed between the top surface of the semiconductor layer and the gate structure. A gate spacer is formed, and physically exposed portions of the semiconductor fin are removed by an anisotropic etch. Subsequently, physically exposed portions of the insulator layer can be etched with a taper. Alternately, a disposable spacer can be formed prior to an anisotropic etch of the insulator layer. The lateral distance between two openings in the dielectric layer across the gate structure is greater than the lateral distance between outer sidewalls of the gate spacers. Selective deposition of a semiconductor material can be performed to form raised active regions.

Claims14

Dependent claims

-10. (canceled)

A method of forming a semiconductor structure comprising:

providing a structure including a semiconductor material layer, an insulator layer contacting a portion of a top surface of said semiconductor material layer, a semiconductor fin overlying a portion of said insulator layer, a gate stack straddling said semiconductor fin, and a gate spacer that is present around said gate stack;
removing physically exposed portions of said semiconductor fin, wherein a remaining portion of said semiconductor fin has a first end surface that is vertically coincident with a first outer sidewall of said gate spacer and a second end surface that is vertically coincident with a second outer sidewall of said gate spacer;
and
forming a first opening and a second opening extending to said semiconductor material layer through said insulator layer, wherein a lateral offset distance between a bottom periphery of said first opening and said first end surface is the same as a lateral offset distance between a bottom periphery of said second opening and said second end surface.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

14/948,977Filed 23 Nov 2015

Priority

12 Jul 2013

Published

17 Mar 2016

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 62/115
Isolations within a component, i.e. internal isolations: dielectric isolations, e.g. air gaps
H10D 64/015
Manufacture or treatment: removing at least parts of gate spacers, e.g. disposable spacers

Partial fin on oxide for improved electrical isolation of raised active regions

Life of this patent

Partial fin on oxide for improved electrical isolation of raised active regions

Life of this patent

Abstract

Claims14