Drain Extended CMOS with Counter-Doped Drain Extension

A method of designing an integrated circuit containing a DEMOS transistor, comprising:

• determining the control of doping of a manufacturing tool;
• choosing a counterdoping concentration of a second doping type;
• calculating a concentration of a first dopant type based upon said control;
• checking the manufacturability of said first dopant type and said counterdoping concentration;
• adjusting said counterdoping concentration to meet a manufacturability requirement if needed;
• calculating a depletion width of a drift region that supports a specified voltage for said DEMOS transistor.
• calculating the design length of said drift region to be 1.1 times said depletion width.

A method of fabricating an integrated circuit, comprising the step of:

• forming a gate of a DEMOS transistor over a substrate;
• forming a source and drain of the DEMOS transistor in the substrate;
• forming a drift region the DEMOS transistor between the gate and drain by:
• implanting a first dopant type into a region of the substrate;
• and
• adding a concentration of scattering centers by counterdoping the region with a second dopant type, wherein at least 10 percent of a length of said drift region between said gate and said drain consists of a concentration of a first dopant type plus a concentration of scattering centers;
• and
• wherein said concentration of said scattering centers is greater than said concentration of said first dopant type divided by 5.