US 2016/0079391 A1 · METHOD OF FABRICATING A VERTICAL MOS TRANSISTOR

Abstract

The disclosure relates to a method of fabricating a vertical MOS transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.

Claims20

Dependent claims

A method, comprising:

forming a vertical MOS transistor, the forming of the MOS transistor including:
forming, above a semiconductor surface, a dielectric layer and a conductive layer in the dielectric layer;
etching a hole through the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface;
forming a gate dielectric on the inner lateral edge of the conductive layer and a bottom dielectric on the portion of the semiconductor surface;
forming an etch-protection semiconductor sidewall on a lateral edge of the hole, the sidewall covering the gate dielectric and an outer region of the bottom dielectric, leaving an inner region of the bottom dielectric exposed;
etching the exposed inner region of the bottom dielectric until the semiconductor surface is reached;
and
depositing a semiconductor material in the hole.

5 more elements

A method of forming a vertical MOS transistor, comprising:

forming a doped region including dopants of a first conductivity type in a semiconductor substrate;
forming a dielectric layer above a surface of the semiconductor substrate;
forming a conductive layer in the dielectric layer;
forming a hole through the conductive layer, the hole exposing through a sidewall surface an inner lateral edge of the conductive layer, and the hole exposing through a bottom surface a portion of the surface of the semiconductor substrate;
forming a gate dielectric on the inner lateral edge of the conductive layer and a bottom dielectric on the exposed portion of the surface of the semiconductor substrate;
forming a protection sidewall on the sidewall surface of the hole, the protection sidewall covering the gate dielectric and the protection sidewall also covering an outer portion of the bottom dielectric, the protection sidewall leaving an inner portion of the bottom dielectric exposed;
removing the exposed inner portion of the bottom dielectric to expose the portion of the surface of the semiconductor substrate;
forming a semiconductor material in the hole;
diffusing the dopants from the doped region into the semiconductor material in the hole to form a first conduction terminal;
implanting dopants of the first conductivity type into an upper surface of the semiconductor material;
and
diffusing the dopants into the hole to form a second conduction terminal, wherein a portion of the semiconductor material between the first and second conduction terminals forms a channel region of the vertical MOS transistor.

9 more elements

Dependencies are inferred from the claim text.

Method of fabricating a vertical mos transistor

Life of this patent

Method of fabricating a vertical mos transistor

Life of this patent

Abstract

Claims20