Method of Tuning Doping Concentration in III-V Compound Semiconductor through Co-Doping Donor and Acceptor Impurities
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHuicheng Chang, Hung-Ta Lin, Meng-Ku Chen, Pang-Yen Tsai
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Abstract
A method includes epitaxially growing a first III-V compound semiconductor, wherein the first III-V compound semiconductor is of p-type. The first III-V compound semiconductor is grown using precursors including a first precursor comprising Cp2Mg, and a second precursor comprising a donor impurity. A second III-V compound semiconductor is grown overlying and contacting the first III-V compound semiconductor. The second III-V compound semiconductor is of n-type.
Claims20
An integrated circuit device comprising:
- a first In-V compound semiconductor region comprising magnesium and a donor impurity selected from the group consisting essentially of silicon, germanium, selenium, tellurium, and combinations thereof, wherein the first In-V compound semiconductor region is of p-type;
- and
- a second In-V compound semiconductor layer overlying and contacting the first In-V compound semiconductor region, wherein the second In-V compound semiconductor layer is free from magnesium, and the second In-V compound semiconductor layer is of n-type.
An integrated circuit device comprising:
- a semiconductor substrate;
- Shallow Trench Isolation (STI) regions in the semiconductor substrate;
- a first III-V compound semiconductor region comprising a first portion higher than top surfaces of the STI regions, wherein the first portion comprises magnesium and a donor impurity;
- a second III-V compound semiconductor layer comprising a first portion overlying and contacting the first III-V compound semiconductor region, wherein the second III-V compound semiconductor layer is free from magnesium and the donor impurity;
- a gate dielectric overlapping the second III-V compound semiconductor layer;
- and
- a gate electrode over the gate dielectric.
An integrated circuit device comprising:
- a semiconductor substrate;
- Shallow Trench Isolation (STI) regions in the semiconductor substrate;
- a first III-V compound semiconductor region comprising a portion higher than top surfaces of the STI regions, wherein the portion comprises magnesium and a donor impurity, and is of p-type, and a net p-type impurity concentration in the portion of the first III-V compound semiconductor region is lower than about 1E17/cm3;
- a gate dielectric overlapping the first III-V compound semiconductor region;
- and
- a gate electrode over the gate dielectric.
Dependencies are inferred from the claim text.