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US 2016/0079309 A1Published application
Resistance change memory, method of manufacturing resistance change memory, and fet
AssigneeKabushiki Kaisha Toshiba
InventorsKensuke OTA, Masumi Saitoh
Life of this patent
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Abstract
According to one embodiment, a resistance change memory includes a first conductive line, a second conductive line provided above the first conductive line, and extending in a first direction, a third conductive line extending in a second direction intersecting the first direction, a select transistor provided between the first and third conductive lines, and a resistance change layer provided between the second and third conductive lines.
Claims15
A resistance change memory comprising:
- a first conductive line;
- a second conductive line provided above the first conductive line, and extending in a first direction;
- a third conductive line extending in a second direction intersecting the first direction;
- a select transistor provided between the first and third conductive lines;
- and
- a resistance change layer provided between the second and third conductive lines,
- wherein the select transistor includes:
- a first conductive layer provided on the first conductive line;
- a first semiconductor layer as a channel including crystal grains, the first semiconductor layer being provided on the first conductive layer;
- a second conductive layer provided on the first semiconductor layer, and connected to the third conductive line;
- and
- a fourth conductive line as a gate extending in the first direction, the fourth conductive line facing to the first semiconductor layer and being provided between the first and second conductive lines,
- wherein the first conductive layer and the first semiconductor layer include a predetermined impurity with a first impurity concentration and the second conductive layer includes no predetermined impurity or the predetermined impurity with a second impurity concentration less than the first impurity concentration.
10 more elements
An FET comprising:
- a substrate;
- a first conductive layer provided above the substrate;
- a first semiconductor layer as a channel including crystal grains, the first semiconductor layer being provided on the first conductive layer;
- a second conductive layer provided on the first semiconductor layer;
- and
- a gate electrode extending in a parallel direction parallel to an upper surface of the substrate,
- wherein the first conductive layer and the first semiconductor layer include a predetermined impurity with a first impurity concentration and the second conductive layer includes no predetermined impurity or the predetermined impurity with a second impurity concentration less than the first impurity concentration.
4 more elements
Dependencies are inferred from the claim text.