Semiconductor memory device and manufacturing method thereof
AssigneeKabushiki Kaisha Toshiba
InventorYuichi ITO
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a semiconductor memory device includes a magnetic tunnel junction (MTJ) element includes a first magnetic layer, a second magnetic layer and a non-magnetic layer between the first and second magnetic layers, a contact layer formed underneath the MTJ element, the contact layer being formed of a first material, and a first layer formed around the contact layer, wherein the first layer in contact with a side surface of the contact layer, has a first width extending parallel to a stacking direction of the MTJ element, and a second width extending perpendicularly to the direction of extension of the first width, the second width being less than the first width.
Claims26
A semiconductor memory device comprising:
- a magnetic tunnel junction (MTJ) element comprising a first magnetic layer, a second magnetic layer and a non-magnetic layer between the first and second magnetic layers;
- a contact layer formed underneath the MTJ element, the contact layer being formed of a first material;
- and
- a first layer formed around the contact layer,
- wherein
- the first layer in contact with a side surface of the contact layer, has a first width extending parallel to a stacking direction of the MTJ element, and a second width extending perpendicularly to the direction of extension of the first width, the second width being less than the first width.
A semiconductor memory device comprising:
- a transistor formed within a semiconductor substrate, the transistor comprising a first diffusion layer, a second diffusion layer and a gate electrode;
- a contact layer formed on the first diffusion layer of the transistor, the contact layer being formed of a first material;
- a first layer formed around the contact layer;
- and
- a magnetic tunnel junction (MTJ) element formed at least on the contact layer,
- wherein
- the first layer in contact with a side surface of the contact layer, has a first width extending parallel to a stacking direction of the MTJ element, and a second width extending perpendicularly to the direction of extension the first width, the second width being less than the first width.
A method of manufacturing a semiconductor memory device, the method comprising:
- forming a transistor within a semiconductor substrate, the transistor comprising a first diffusion layer, a second diffusion layer and a gate electrode;
- forming a contact layer on the first diffusion layer of the transistor, the contact layer being formed of a first material;
- forming a first layer around the contact layer;
- and
- forming a magnetic tunnel junction (MTJ) element on the contact layer.
Dependencies are inferred from the claim text.