Method of manufacturing a semiconductor device with an isolation region and a device manufactured by the method
AssigneeNXP B.V.
InventorJan Sonsky
Life of this patent
Estimating the term…
Abstract
A method of manufacturing a semiconductor device includes forming trench isolation structures, exposing some of the trench isolation structures 28 to leave others 30 masked, and then selectively etching a buried layer to form a cavity 32 under an active device region 34. The active device region 34 is supported by support regions in the exposed trenches 28. The buried layer may be a SiGe layer on a Si substrate.
Claims11
1-16. (canceled)
A semiconductor device, comprising:
- a semiconductor substrate;
- a buried insulating layer over a part of the semiconductor substrate;
- a buried semiconductor layer of different material to the substrate over the remainder of the semiconductor substrate;
- a device layer over the buried insulating layer and buried semiconductor layer;
- a plurality of trench isolation structures filled with insulator extending through the full thickness of the device layer to define at least one insulated active device region in the device layer surrounded by a trench isolation structure and above the buried insulating layer, the insulated active device region being insulated from the substrate by the buried insulating layer and the trench isolation structure;
- and
- at least one substrate-connected device region in the device layer connected to the substrate through buried semiconductor layer.
A semiconductor device comprising:
- a substrate of a first semiconductor material;
- a buried layer of a second semiconductor material on the substrate;
- a device layer of a third semiconductor material on the second semiconductor material, wherein at least one active region is partially present in the device layer and over the buried layer;
- trenches that extend at least partially through the device layer;
- a plurality of trench isolation regions spaced laterally across the device layer and configured and arranged on sides of at least one isolated active region, the trench isolation regions including at least one trench at least partially filled with support insulator, and including at least one other trench that is lined with support insulator that defines an etched pathway which leads to and exposes at least part of the buried layer;
- and
- wherein the buried layer has been selectively etched through the part of the trench not including the support insulator to remove the buried layer from under at least one isolated region of the device layer leaving the support insulator for acting as a support structure to support the isolated region.
A semiconductor device comprising:
- a substrate of a first semiconductor material;
- a buried layer of a second semiconductor material on the substrate;
- a device layer of a third semiconductor material on the second semiconductor material, wherein at least one active region is at least partially formed in the device layer and over the buried layer;
- trenches extending at least partially through the device layer;
- a plurality of trench isolation structures spaced laterally across the device layer, the trench isolation structures comprising at least one trench including support insulator, with insulator material, partially filling the at least one trench but with at least part of the buried layer exposed through the trench;
- at least one masked trench region leaving at least one trench isolation structure exposed as at least one exposed trench region;
- at least one exposed trench region having no support insulator therein and with the insulator material defining a pathway that leads to and exposes at least part of the buried layer;
- wherein the buried layer is through at least one other trench and the etched pathway and
- wherein the buried layer has been removed from under at least one active region of the device layer, thereby leaving the support insulator for acting as a support structure to support the at least one active region.
The semiconductor device as recited in 23, there is at least one power semiconductor component in the at least one active region and at least one control or logic semiconductor component in the substrate-connected active region.
Dependencies are inferred from the claim text.