Fully-depleted silicon-on-insulator transistors
AssigneeInternational Business Machines Corporation
InventorsTerence B. HOOK, Horacio MENDEZ
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Abstract
A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold voltage and each being over an n-well that is biased to a first voltage; and a first NFET, a second NFET, and a third NFET each having a different threshold voltage and each being over a p-type substrate that is biased to a second voltage. The second voltage is different than the first voltage.
Claims20
A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure, comprising:
- a first PFET, a second PFET, and a third PFET each having a different threshold voltage and each being over an n-well that is biased to a first voltage;
- and
- a first NFET, a second NFET, and a third NFET each having a different threshold voltage and each being over a p-type substrate that is biased to a second voltage,
- wherein the second voltage is different than the first voltage.
A semiconductor structure, comprising:
- a substrate;
- a well in the substrate and biased differently than the substrate;
- a buried oxide (BOX) layer on the substrate;
- a first PFET having a first threshold voltage;
- a second PFET having a second threshold voltage less than the first threshold voltage;
- a third PFET having a third threshold voltage less than the second threshold voltage;
- a first NFET having a fourth threshold voltage;
- a second NFET having a fifth threshold voltage less than the fourth threshold voltage;
- and
- a third NFET having a sixth threshold voltage less than the fifth threshold voltage,
- wherein the first PFET, the second PFET, and the third PFET are on the BOX layer and over the well, and
- the first NFET, the second NFET, and the third NFET are on the BOX layer and over substrate.
A method of manufacturing a semiconductor structure, comprising:
- forming a well in a substrate;
- forming a first PFET, a second PFET, and a third PFET on a buried oxide (BOX) layer and over the well;
- forming a first NFET, a second NFET, and a third NFET on the BOX layer and over the substrate;
- biasing the well to a first voltage;
- and
- biasing the substrate to a second voltage different than the first voltage,
- wherein the first PFET, the second PFET, and the third PFET each has a different threshold voltage, and
- the first NFET, the second NFET, and the third NFET each has a different threshold voltage.
Dependencies are inferred from the claim text.