Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same

A method for manufacturing an integrated circuit within a semiconductor chip, comprising:

• forming a plurality of transistors within a region of the semiconductor chip, each of the plurality of transistors in the region forming part of circuitry associated with execution of one or more logic functions, the plurality of transistors having respective gate electrodes formed by some of at least nine conductive structures present within the region,
• wherein forming the plurality of transistors includes forming each of the at least nine conductive structures to respectively have a corresponding top surface, wherein an entirety of a periphery of the corresponding top surface is defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the corresponding top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,
• wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end,
• wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding second end,
• wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end,
• wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding second end,
• wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first and second edges,
• wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within the space between the corresponding first and second edges,
• the top surfaces of the at least nine conductive structures co-planar with each other,
• each of the at least nine conductive structures having a corresponding lengthwise centerline oriented in a first direction along its top surface and extending from its first end to its second end,
• each of the at least nine conductive structures having a length as measured along its lengthwise centerline from its first end to its second end,
• wherein the first edge of each of the at least nine conductive structures is substantially straight,
• wherein the second edge of each of the at least nine conductive structures is substantially straight,
• each of the at least nine conductive structures having both its first edge and its second edge oriented substantially parallel to its lengthwise centerline,
• each of the at least nine conductive structures having a width measured in a second direction perpendicular to the first direction at a midpoint of its lengthwise centerline, each of the first direction and the second direction oriented substantially parallel to the co-planar top surfaces of the at least nine conductive structures,
• wherein forming the plurality of transistors includes positioning the at least nine conductive structures in a side-by-side manner such that each of the at least nine conductive structures is positioned to have at least a portion of its length beside at least a portion of the length of another of the at least nine conductive structures,
• wherein the width of each of the at least nine conductive structures is less than 45 nanometers, each of the at least nine conductive structures positioned such that a distance as measured in the second direction between its lengthwise centerline and the lengthwise centerline of at least one other of the at least nine conductive structures is substantially equal to a first pitch that is less than or equal to about 193 nanometers,
• wherein the at least nine conductive structures includes a first conductive structure, the first conductive structure including a portion that forms a gate electrode of a first transistor of a first transistor type, the first conductive structure also including a portion that forms a gate electrode of a first transistor of a second transistor type,
• wherein the at least nine conductive structures includes a second conductive structure, the second conductive structure including a portion that forms a gate electrode of a second transistor of the first transistor type, wherein any transistor having its gate electrode formed by the second conductive structure is of the first transistor type,
• wherein the at least nine conductive structures includes a third conductive structure, the third conductive structure including a portion that forms a gate electrode of a second transistor of the second transistor type, wherein any transistor having its gate electrode formed by the third conductive structure is of the second transistor type,
• wherein the at least nine conductive structures includes a fourth conductive structure, the fourth conductive structure including a portion that forms a gate electrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth conductive structure is of the first transistor type,
• wherein the at least nine conductive structures includes a fifth conductive structure, the fifth conductive structure including a portion that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth conductive structure is of the second transistor type,
• wherein the at least nine conductive structures includes a sixth conductive structure, the sixth conductive structure including a portion that forms a gate electrode of a fourth transistor of the first transistor type, the sixth conductive structure also including a portion that forms a gate electrode of a fourth transistor of the second transistor type,
• wherein the first transistor of the first transistor type includes a first diffusion terminal and the second transistor of the first transistor type includes a first diffusion terminal, the first diffusion terminal of the first transistor of the first transistor type electrically connected to the first diffusion terminal of the second transistor of the first transistor type through a first electrical connection,
• wherein the first transistor of the second transistor type includes a first diffusion terminal, and the second transistor of the second transistor type includes a first diffusion terminal, the first diffusion terminal of the first transistor of the second transistor type electrically connected to the first diffusion terminal of the second transistor of the second transistor type through a second electrical connection,
• wherein the second transistor of the first transistor type includes a second diffusion terminal, and the third transistor of the first transistor type includes a first diffusion terminal, the second diffusion terminal of the second transistor of the first transistor type electrically connected to the first diffusion terminal of the third transistor of the first transistor type through a third electrical connection,
• wherein the second transistor of the second transistor type includes a second diffusion terminal, and the third transistor of the second transistor type includes a first diffusion terminal, the second diffusion terminal of the second transistor of the second transistor type electrically connected to the first diffusion terminal of the third transistor of the second transistor type through a fourth electrical connection,
• wherein the third transistor of the first transistor type includes a second diffusion terminal, and the fourth transistor of the first transistor type includes a first diffusion terminal, the second diffusion terminal of the third transistor of the first transistor type electrically connected to the first diffusion terminal of the fourth transistor of the first transistor type through a fifth electrical connection,
• wherein the third transistor of the second transistor type includes a second diffusion terminal, and the fourth transistor of the second transistor type includes a first diffusion terminal, the second diffusion terminal of the third transistor of the second transistor type electrically connected to the first diffusion terminal of the fourth transistor of the second transistor type through a sixth electrical connection,
• wherein the third electrical connection is electrically connected to the fourth electrical connection through a seventh electrical connection,
• wherein the gate electrode of the second transistor of the first transistor type is electrically connected to the gate electrode of the third transistor of the second transistor type through an eighth electrical connection,
• wherein the gate electrode of the third transistor of the first transistor type is electrically connected to the gate electrode of the second transistor of the second transistor type through a ninth electrical connection,
• wherein the lengthwise centerline of the second conductive structure is substantially aligned with the lengthwise centerline of the third conductive structure,
• wherein the lengthwise centerline of the fourth conductive structure is separated from the lengthwise centerline of the fifth conductive structure by a distance greater than zero as measured in the second direction, and
• wherein each transistor of the first transistor type having its gate electrode formed by any of the at least nine conductive structures is included in a first collection of transistors, and wherein each transistor of the second transistor type having its gate electrode formed by any of the at least nine conductive structures is included in a second collection of transistors, wherein the first collection of transistors is separated from the second collection of transistors by an inner sub-region of the region, wherein the inner sub-region does not include a source or a drain of any transistor.