Transistors, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions

A transistor, comprising:

• gate dielectric directly against a channel region;
• a first conductive gate portion along a first segment of the channel region, and spaced from said first segment by at least the gate dielectric;
• a second conductive gate portion along a second segment of the channel region, and spaced from said second segment by at least the gate dielectric;
• the second segment being adjacent the first segment;
• the second conductive gate portion comprising a different composition from the first conductive gate portion and being directly against the first conductive gate portion;
• and
• wherein one of the first and second gate portions consists of conductively-doped silicon and the other of the first and second gate portions comprises metal.

A semiconductor construction, comprising:

• a channel region;
• gate dielectric directly against the channel region;
• the gate dielectric comprising one or more oxides;
• a semiconductor-containing gate portion along a first segment of the channel region and spaced from said first segment by at least the gate dielectric;
• the semiconductor-containing gate portion consisting of conductively-doped semiconductor material;
• a metal-containing gate portion along a second segment of the channel region and spaced from said second segment by at least the gate dielectric;
• the second segment being adjacent the first segment;
• the metal-containing gate portion being directly against the semiconductor-containing gate portion;
• and
• the semiconductor-containing gate portion, metal-containing gate portion, dielectric material and channel region comprising a transistor.

A semiconductor construction, comprising:

• a channel region over an upper surface of a silicon-containing base and extending substantially vertically relative to such upper surface;
• gate dielectric directly against the channel region;
• a semiconductor-containing gate portion along a first segment of the channel region and spaced from said first segment by at least the gate dielectric;
• the semiconductor-containing gate portion consisting of conductively-doped semiconductor material;
• a metal-containing gate portion along a second segment of the channel region and spaced from said second segment by at least the gate dielectric;
• the second segment being adjacent the first segment;
• the metal-containing gate portion being directly against the semiconductor-containing gate portion;
• the semiconductor-containing gate portion, metal-containing gate portion, dielectric material and channel region comprising a transistor;
• and
• a NAND string electrically coupled with the transistor.

A method of forming a semiconductor construction, comprising:

• forming vertically-stacked memory cells along a vertically-extending channel material;
• forming an insulative material over the channel material;
• forming a first semiconductor material over the insulative material;
• forming metal-containing material over the first semiconductor material;
• forming a first opening to extend through the metal-containing material and the first semiconductor material to the insulative material;
• forming a gate dielectric along sidewalls and a bottom of the first opening;
• forming a second opening through the gate dielectric at the bottom of the first opening and through the insulative material;
• and
• forming second semiconductor material within the first and second openings;
• a portion of the second semiconductor material within the first opening being spaced from the first semiconductor material and the metal-containing material by at least the gate dielectric and being a transistor channel region.