Non-volatile semiconductor memory device and manufacturing method thereof
AssigneeKabushiki Kaisha Toshiba
InventorsYoshihiro AKUTSU, Ryota Katsumata
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AssigneeKabushiki Kaisha Toshiba
InventorsYoshihiro AKUTSU, Ryota Katsumata
Estimating the term…
This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.
A non-volatile semiconductor memory device, comprising:
A manufacturing method of a non-volatile semiconductor memory device, wherein
Dependencies are inferred from the claim text.