Semiconductor integrated circuit device
AssigneeRenesas Electronics Corporation
InventorsKazuo Sakamoto, Naozumi Morino, Kazuo Tanaka, Hiroyasu Ishizuka
Life of this patent
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Abstract
A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.
Claims10
1-8. (canceled)
A semiconductor integrated circuit device, comprising:
- a plurality of bonding pads arranged in a first direction, each of the bonding pads having a first width in the first direction;
- a plurality of I/O cells arranged in first direction, each of the I/O cells being disposed under an associated one of the bonding pads in plan view and having a second width in the first direction,
- wherein each of the I/O cells includes an I/O logic circuit arranged in an I/O logic region and an I/O buffer circuit arranged in an I/O buffer region adjacent in the first direction to the I/O logic region,
- wherein the second width is smaller than the first width.
Dependencies are inferred from the claim text.