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US 2016/0079230 A1Published application
Fast and stable ultra low drop-out (ldo) voltage clamp device
AssigneeFairchild Semiconductor Corporation
InventorsAdrian MIKOLAJCZAK, Tirthajyoti SARKAR
Life of this patent
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Abstract
In one general aspect, an apparatus can include a junction-less, gate-controlled voltage clamp device having a gate terminal coupled to a voltage reference device.
Claims20
An apparatus, comprising:
- a voltage reference device;
- and
- a junction-less, gate-controlled voltage clamp device configured to limit a current and having a gate terminal coupled to the voltage reference device.
An apparatus, comprising:
- a semiconductor substrate;
- a trench defined within the semiconductor substrate and having a depth aligned along a vertical axis, a length aligned along a longitudinal axis, and a width aligned along a horizontal axis;
- a dielectric disposed within the trench;
- and
- a gate electrode disposed within the dielectric and insulated from the semiconductor substrate by the dielectric,
- the semiconductor substrate having a portion aligned vertically and adjacent the trench, the portion of the semiconductor substrate having a conductivity type that is continuous along an entirety of the depth of the trench and excludes a junction of two different conductivity type materials in a primary current path.
3 more elements
Dependencies are inferred from the claim text.