Semiconductor package assembly

A semiconductor package assembly, comprising:

• a first semiconductor package, comprising:
• a semiconductor die having pads thereon;
• first vias disposed on the first semiconductor die, coupled to the pads;
• and
• a second semiconductor package stacked on the first semiconductor package, comprising:
• a body having a die-attach surface and a bump-attach surface opposite to the die-attach surface;
• a first dynamic random access memory (DRAM) die mounted on the bump-attach surface, coupled to the body;
• and
• a second dynamic random access memory (DRAM) die mounted on the die-attach surface, coupled to the body through the bonding wires,
• wherein a number of input/output (I/O) pins of first DRAM die is different from a number of input/output (I/O) pins of the second DRAM die.

A semiconductor package assembly, comprising:

• a system-on-chip (SOC) package, comprising:
• a logic die having first pads thereon;
• a first redistribution layer (RDL) structure coupled to the logic die;
• and
• a molding compound surrounding the logic die, being in contact with the first RDL structure and the logic die;
• and
• a dynamic random access memory (DRAM) package stacked on the SOC package, comprising:
• a body having a die-attach surface and a bump-attach surface opposite to the die-attach surface;
• and
• a dynamic random access memory (DRAM) die mounted on the die-attach surface, coupled to the body through the bonding wires,
• wherein one of the SOC package and the DRAM package further comprises an additional dynamic random access memory (DRAM) die embedded therein,
• wherein the additional DRAM die has through silicon via (TSV) interconnects formed through the additional DRAM die.