Semiconductor device

A semiconductor device comprising:

• an interposer;
• a logic chip mounted on a first principal surface of the interposer;
• a memory chip mounted on a second principal surface of the interposer, the second principal surface is a principal surface arranged on an opposite side of the first principal surface;
• and
• a package substrate on which the logic chip, the interposer, and the memory chip are mounted,
• the interposer including:
• a substrate;
• a first via configured to electrically connect a signal terminal of the logic chip and a signal terminal of the memory chip to each other through the substrate;
• a second via to which a power supply terminal of the logic chip is electrically connected through the substrate;
• a multi-layer wiring, to which the second via is electrically connected, disposed on the second principal surface side of the substrate;
• and
• a third via configured to be electrically connected to the power supply terminal of the logic chip through the substrate, the second via and the multi-layer wiring, a metal wire being connected to a portion on a side of the first principal surface in the third via,
• the package substrate including a power supply wiring, and
• the third via and the power supply wiring being electrically connected to each other through the metal wire.

A semiconductor device comprising:

• an interposer;
• a logic chip mounted on a first principal surface of the interposer;
• a memory chip mounted on a second principal surface of the interposer, the second principal surface is a principal surface arranged on an opposite side of the first principal surface;
• and
• a package substrate on which the logic chip, the interposer, and the memory chip are mounted,
• the interposer including:
• a substrate;
• a first via configured to electrically connect a signal terminal of the logic chip and a signal terminal of the memory chip to each other through the substrate;
• a multi-layer wiring, to which a power supply terminal of the logic chip is electrically connected, disposed on the first principal surface side of the substrate;
• and
• a fourth via configured to be electrically connected to the power supply terminal of the logic chip through the substrate and the multi-layer wiring, a metal pillar being connected to a portion on a side of the second principal surface in the fourth via,
• the metal pillar extending in a direction that is approximately perpendicular to the second principal surface,
• the package substrate including a power supply wiring, and
• the fourth via and the power supply wiring being electrically connected to each other through the metal pillar.