Semiconductor device and a method of manufacturing the same
AssigneeRenesas Electronics Corporation
InventorShinya Suzuki
Life of this patent
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Abstract
A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.
Claims9
1-18. (canceled)
A semiconductor device comprising:
- (a) a semiconductor substrate of a substantially rectangular shape;
- (b) a semiconductor element formed on a main surface of the semiconductor substrate;
- (c) a multilayer wiring structure formed over the semiconductor element;
- (d) a first pad electrode and a second pad electrode which are formed in a same layer as an uppermost layer of the multilayer wiring structure;
- (e) dummy patterns being formed in the same layer as the uppermost layer of the multilayer wiring structure and being disposed at a different area from the first pad electrode and the second pad electrode in plan view;
- (f) a first insulating film being formed over the first pad electrode, the second pad electrode, and the dummy patterns and having a first opening and a second opening, the first opening and the second opening being located at upper surfaces of the first pad electrode and the second pad electrode respectively;
- and
- (g) a first bump electrode and a second bump electrode being formed over the first insulating film and being electrically connected to the first pad electrode and the second pad electrode respectively via the first opening and the second opening,
- wherein the first bump electrode and the second bump electrode are adjacently arranged in a first direction which is along one long edge of the semiconductor substrate,
- wherein the dummy patterns are disposed at a different area from the first bump electrode and the second bump electrode in plan view, and
- wherein the dummy patterns are located between the first bump electrode and the second bump electrode in plan view.
Dependencies are inferred from the claim text.