Traceable integrated circuits and production method thereof
AssigneeSTMicroelectronics S.r.l.
InventorAlberto Pagani
Life of this patent
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Abstract
An embodiment of a method for producing traceable integrated circuits includes forming on a wafer of semiconductor material functional regions for implementing specific functionalities of corresponding integrated circuits, forming at least one seal ring around each functional region of the corresponding integrated circuit, and forming on each integrated circuit at least one marker indicative of information of the integrated circuit. Forming on each integrated circuit at least one marker may include forming the at least one marker on at least a portion of the respective seal ring that is visible.
Claims21
A method, comprising:
- forming on a wafer of semiconductor material including a plurality of die locations a functional region at each die location for implementing specific functionalities of a corresponding integrated circuit;
- forming a seal ring around the functional region of each integrated circuit, and
- forming on a top surface of each seal ring at least one marker that provides die information.
A method, comprising:
- forming on a wafer of semiconductor material including a plurality of die locations a functional region at each die location for implementing specific functionalities of a corresponding integrated circuit;
- forming a seal ring around the functional region of each integrated circuit, said seal ring including a stack of interconnected layers, said stack including a top layer having a thickness;
- and
- forming a groove in a top surface of said top layer, said groove positioned in between and away from an inner and outer perimeter edge of the seal ring and having a depth that is less than said thickness, said groove providing die information.
A method, comprising:
- forming on a wafer of semiconductor material including a plurality of die locations a functional region at each die location for implementing specific functionalities of a corresponding integrated circuit;
- forming a seal ring around the functional region of each integrated circuit, said seal ring including a stack of interconnected layers including a top layer made of a first metal material having a first visible color;
- forming a cover layer on the top layer, said cover layer made of a second metal material having a second visible color different from the first visible color and having a thickness;
- and
- forming a groove in the cover layer, said groove positioned in between and away from an inner and outer perimeter edge of the seal ring and having a depth that is at least said thickness, said groove providing die information.
Dependencies are inferred from the claim text.