Tie-off structures for middle-of-line (mol) manufactured integrated circuits, and related methods

A middle-of-line (MOL) stack in an integrated circuit (IC), comprising:

• a substrate;
• a gate structure of a transistor overlying the substrate, the gate structure comprising:
• a gate region coupled to the substrate;
• and
• a metal gate connection overlying the gate region;
• a first metal layer overlying the substrate, the first metal layer coupled to one of a drain or source of the transistor;
• a dielectric layer overlying the gate structure and the first metal layer;
• and
• a means for electrically coupling the metal gate connection to the first metal layer, the means for electrically coupling disposed in and above the dielectric layer.

A method of forming a middle-of-line (MOL) stack in an integrated circuit (IC), comprising:

• during a front-end-of-line (FEOL) process, providing a substrate;
• during the FEOL process, providing a gate structure of a transistor overlying the substrate, the gate structure comprising:
• a gate region coupled to the substrate;
• and
• a metal gate connection overlying the gate region;
• during the FEOL process, providing a first metal layer overlying the substrate, the first metal layer coupled to one of a drain or source of the transistor;
• during the FEOL process, providing a dielectric layer overlying the gate structure and the first metal layer;
• during a middle-of-line (MOL) process, providing a metal structure disposed in and above the dielectric layer;
• and
• coupling the metal gate connection and the first metal layer with the metal structure.

A middle-of-line (MOL) stack in an integrated circuit (IC), comprising:

• a transistor comprising a gate and at least one of a source and a drain;
• a first metal layer coupled to the at least one of the source and the drain;
• a gate connection coupled to the gate;
• a dielectric layer above the transistor, the first metal layer and the gate connection;
• and
• a metal structure positioned in and above the dielectric layer electrically coupling the first metal layer with the gate connection.