Preparation method of three-dimensional integrated inductor-capacitor structure

A method for preparing a three-dimensional integrated inductor-capacitor structure, comprising:

• Step S1, providing a semiconductor substrate, and preparing a first insulating layer and an underlying metal thin film layer sequentially on said semiconductor substrate, and removing the underlying metal thin film layer partially to form several parallel arranged bottom metal conducting wires over said first insulating layer;
• Step S2, preparing a second insulating layer covering an exposed surface of said bottom metal conducting wires and said first insulating layer, and etching said second insulating layer to form a first through hole on both ends which extend along the length direction of each of said bottom metal conducting wires;
• Filling first metal in said first through hole to form two columns of first metal interconnections on said bottom metal conducting wires;
• Step S3, preparing third insulating layer covering an upper surface of said first metal interconnections and second insulating layer, and etching the third insulating layer to form a second through hole and several annular grooves over each of said first metal interconnections, and at least two said annular grooves surrounding the each of the second through holes;
• Filling second metal in said second through hole and annular grooves to form second metal interconnections and a number of annular magnetic cores on each of said first metal interconnections;
• Step S4, preparing a fourth insulating layer covering upper surfaces of said second metal interconnections, said magnetic cores and said third insulating layer, and etching the fourth insulating layer to form a third through hole above each of said second metal interconnections and a fourth through hole above each of said magnetic cores;
• Filling third metal in said third through hole and fourth through hole to form third metal interconnections in said third through hole and fourth metal interconnections in said fourth through hole;
• Step S5, preparing a top metal thin film covering upper surfaces of said third metal interconnections, said fourth metal interconnections and fourth insulating layer;
• and etching said top metal thin film to form a number of leading wires and a number of top metal conducting wires arranged in parallel;
• Wherein each of said leading wires are connected to said magnetic cores through said fourth metal interconnections, said top metal conducting wires connect said bottom metal conducting wires end to end in sequence through said third metal interconnections, said second metal interconnections and said first metal interconnections in turn.