Semiconductor device, layout of semiconductor device, and method of manufacturing semiconductor device

A layout of a semiconductor device, the layout comprising:

• an active area;
• a metal zero layer, comprising:
• a lower metal layer over the active area, and
• an upper metal layer overlying the lower metal layer;
• and
• a dielectric layer interposed between the lower metal layer and the overlying upper metal layer in a first region of the metal zero layer, wherein the dielectric layer is absent between the lower metal layer and the overlying upper metal layer in a second region of the metal zero layer.

A method of manufacturing a semiconductor device, the method comprising:

• forming a gate structure over an active area of a substrate;
• forming a lower conductive layer over the active area, the lower conductive layer at least partially co-elevational with the gate structure;
• forming a first dielectric layer over a first region of the lower conductive layer, while exposing a second region of the lower conductive layer;
• and
• forming an upper conductive layer overlying both the first and second regions of the lower conductive layer, wherein the upper conductive layer is in direct electrical contact with the lower conductive layer in the second region and electrically isolated from the lower conductive layer in the first region.