US 2016/0079160 A1 · SEMICONDUCTOR DEVICE

Abstract

The performances of a semiconductor device are improved. A semiconductor device has a first electrode and a dummy electrode formed apart from each other over a semiconductor substrate, a second electrode formed between the first electrode and the dummy electrode, at the circumferential side surface of the first electrode, and at the circumferential side surface of the dummy electrode, and a capacitive insulation film formed between the first electrode and the second electrode. The first electrode, the second electrode, and the capacitive insulation film form a capacitive element. Further, the semiconductor device has a first plug penetrating through the interlayer insulation film, and electrically coupled with the first electrode, and a second plug penetrating through the interlayer insulation film, and electrically coupled with the portion of the second electrode formed at the side surface of the dummy electrode opposite to the first electrode side.

Claims8

Dependent claims

1-20. (canceled)

A method for manufacturing a semiconductor device, including the steps of:

(a) forming a first conductive film over a semiconductor substrate,
(b) patterning the first conductive film, and forming a first electrode formed of the first conductive film, and forming a first dummy electrode formed of the first conductive film apart from the first electrode,
(c) forming a first insulation film over the semiconductor substrate including the surface of the first electrode and the surface of the first dummy electrode,
(d) forming a second conductive film over the first insulation film,
(e) etching back the second conductive film, and leaving the second conductive film between the first electrode and the first dummy electrode, at the circumferential side surface of the first electrode, and at the circumferential side surface of the first dummy electrode via the first insulation film, thereby to form a second electrode,
(f) removing a portion of the first insulation film not covered with the second electrode, and forming a first capacitive insulation film formed of the first insulation film between the first electrode and the second electrode,
(g) forming an interlayer insulation film in such a manner as to cover the first electrode, the second electrode, and the first capacitive insulation film,
(h) forming a first coupling hole penetrating through the interlayer insulation film, and reaching the first electrode, and a second coupling hole penetrating through the interlayer insulation film, and reaching a first portion of the second electrode formed at a side surface of the first dummy electrode opposite to the first electrode side, and
(i) forming a first coupling electrode formed of a third conductive film embedded in the first coupling hole, and electrically coupled with the first electrode, and forming a second coupling electrode formed of the third conductive film embedded in the second coupling hole, and electrically coupled with the first portion of the second electrode,
wherein in the step (f), the first electrode, the second electrode, and the first capacitive insulation film form a first capacitive element.

7 more elements

A method for manufacturing a semiconductor device, including the steps of:

(a) forming a first conductive film over a semiconductor substrate,
(b) patterning the first conductive film, and forming a first electrode formed of the first conductive film,
(c) forming a first insulation film over the first semiconductor substrate including the surface of the first electrode,
(d) forming a second conductive film over the first insulation film,
(e) etching back the second conductive film, an leaving the second conductive film at the circumferential side surface of the first electrode via the first insulation film, thereby to form a second electrode,
(f) removing a portion of the first insulation film not covered with the second electrode, and forming a first capacitive insulation film formed of the first insulation film between the first electrode and the second electrode,
(g) forming an interlayer insulation film in such a manner as to cover the first electrode, the second electrode, and the first capacitive insulation film,
(h) forming a first coupling hole penetrating through the interlayer insulation film, and reaching the first electrode, and a second coupling hole penetrating through the interlayer insulation film, and reaching the second electrode, and
(i) forming a first coupling electrode formed of a third conductive film embedded in the first coupling hole, and electrically coupled with the first electrode, and forming a second coupling electrode formed of the third conductive film embedded in the second coupling hole, and electrically coupled with the second electrode,
wherein, in the step (f), the first electrode, the second electrode, and the first capacitive insulation film form a first capacitive element, and
wherein, in the step (b), the first electrode including a plurality of first line parts respectively extending in a first direction, and arrayed in a second direction crossing with the first direction in plan view is formed of the first conductive film.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application

14/950,987Filed 24 Nov 2015

Priority

JP 2013-11047627 May 2013

Published

17 Mar 2016

Term ends

Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10W 20/496
Capacitive arrangements or effects of, or between wiring layers: capacitor integral with wiring layers
H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10B 43/35
Characterised by the memory core region: with cell select transistors, e.g. NAND
H10D 30/0413
Of FETs having insulated gates [IGFET]: of FETs having charge-trapping gate insulators, e.g. MNOS transistors

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims8