Semiconductor package structure
AssigneeAdvanced Semiconductor Engineering, Inc.
InventorsJen-Kuang FANG, Kuo-Hua CHEN
Life of this patent
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Abstract
The present disclosure relates to a semiconductor package structure, including a die and a package substrate. The die includes a semiconductor substrate, multiple interconnect metal layers, and at least one inter-level dielectric disposed between ones of the interconnect metal layers. Each inter-level dielectric is formed of a low k material. An outermost interconnect metal layer has multiple first conductive segments exposed from a surface of the inter-level dielectric. The package substrate includes a substrate body and multiple second conductive segments exposed from a surface of the substrate body. The second conductive segments are electrically connected to the first conductive segments.
Claims20
A semiconductor package structure, comprising:
- a die, comprising:
- a semiconductor substrate;
- a plurality of interconnect metal layers, disposed adjacent to a surface of the semiconductor substrate;
- and
- at least one inter-level dielectric disposed between ones of the plurality of interconnect metal layers, each inter-level dielectric being formed of a low k material;
- wherein an outermost interconnect metal layer includes a plurality of first conductive segments exposed from a surface of the inter-level dielectric for external connections;
- and
- a package substrate, comprising:
- a substrate body;
- and
- a plurality of second conductive segments disposed adjacent to a surface of the substrate body and exposed from the surface of the substrate body, wherein the second conductive segments are electrically connected to corresponding ones of the first conductive segments.
Dependencies are inferred from the claim text.