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US 2016/0079132 A1Published application
Die testing using top surface test pads
AssigneeTexas Instruments Incorporated
InventorsLee D. Whetsel, Richard L. Antley
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Abstract
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.
Claims7
An integrated circuit comprising:
- (a) die pads;
- (b) a first embedded circuit having an input terminal and an output terminal;
- (c) a first lead coupling the input terminal of the first embedded circuit only to a first die pad;
- (d) a second embedded circuit having an input terminal and an output terminal;
- (e) a second lead coupling the output terminal of the second embedded circuit only to a second die pad separate from the first die pad;
- (f) a third embedded circuit having an input terminal and an output terminal;
- (g) a third lead coupling the output terminal of the first embedded circuit to the input terminal of the third embedded circuit and being unconnected with the die pads;
- (h) a fourth lead coupling the output terminal of the third embedded circuit to the input terminal of the second embedded circuit and being unconnected with the die pads;
- and
- (i) test pads coupled to the third and fourth leads.
7 more elements
Dependencies are inferred from the claim text.