Preventing Delamination and Cracks in Fabrication of Group III-V Devices
AssigneeInfineon Technologies Americas Corp.
InventorMichael A. Briere
Life of this patent
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Abstract
In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at least one device layer over the III-Nitride body. The method also includes etching grid array trenches in the III-Nitride body, where the etching of the grid array trenches may extend into the group IV substrate. The method can also include forming an edge trench around a perimeter of the semiconductor wafer. The method further includes forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.
Claims17
1-14. (canceled)
A method comprising:
- growing a III-Nitride body over a group IV substrate in a semiconductor wafer;
- etching grid array trenches in said III-Nitride body to form a plurality of III-Nitride dies;
- forming at least one device layer over each of said plurality of III-Nitride dies;
- separating said plurality of III-Nitride dies by cutting said semiconductor wafer approximately along said grid array trenches.
A method comprising:
- growing a group III-V body over a group IV substrate in a semiconductor wafer;
- etching trenches in said group III-V body to form a plurality of group III-V dies;
- forming at least one device layer over each of said plurality of group III-V dies;
- separating said plurality of group III-V dies by cutting said semiconductor wafer approximately along said trenches.
Dependencies are inferred from the claim text.