Loading patent…
AssigneeSiliconware Precision Industries Co., Ltd.
InventorsKuan-Wei Chuang, Shih-Kuang Chiu, Chun-Tang Lin, Jung-Pang Huang
Estimating the term…
A semiconductor package is provided, which includes: a carrier; a frame having a plurality of openings, wherein the frame is bonded to the carrier and made of a material different from that of the carrier; a plurality of electronic elements disposed in the openings of the frame, respectively; an encapsulant formed in the openings of the frame for encapsulating the electronic elements; and a circuit layer formed on and electrically connected to the electronic elements. By accurately controlling the size of the openings of the frame, the present invention increases the accuracy of positioning of the electronic elements so as to improve the product yield in subsequent processes.
A semiconductor package, comprising:
A semiconductor package, comprising:
A semiconductor package, comprising:
A carrier structure, comprising:
A carrier structure, comprising:
A carrier structure, comprising:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
No related US applications are recorded in the indexed filing history.
Backward citations are indexed for grants only.
For supporting or gripping: using temporarily an auxiliary support
Characterised by their conductive parts: layouts of interconnections
By depositing layers on the chip or wafer, e.g. "chip-first" RDLs: extending onto an encapsulation that laterally surrounds the chip or wafer,…
Manufacture or treatment: batch processes
Term end not estimated
1. Field of the Invention The present invention relates to semiconductor packages, and more particularly, to a semiconductor package and a fabrication method thereof for improving the product yield.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed toward the trend of multi-function and high performance. Accordingly, wafer level packaging (WLP) technologies have been developed to meet the miniaturization requirement of semiconductor packages.
FIGS. 1A to 1E are schematic cross-sectional view showing a method for fabricating a semiconductor package according to the prior art;
FIGS. 2A to 2E are schematic cross-sectional views showing another method for fabricating a semiconductor package according to the prior art, wherein FIGS. 2B′ and 2E′ show practical structures of FIGS. 2B and 2E, respectively;
FIGS. 3A to 3F are schematic cross-sectional views showing a method for fabricating a semiconductor package according to a first embodiment of the present invention, wherein FIGS. 3C′, 3E′ and 3F′ show another embodiment of FIGS. 3C to 3F, and FIGS. 3D′ and 3D″ are schematic upper views showing different embodiments of FIG. 3D (omitting the circuit layer);
The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification.
It should be noted that all the drawings are not intended to limit the present invention. Various modifications and variations can be made without departing from the spirit of the present invention. Further, terms such as “on”, “a” etc. are merely for illustrative purposes and should not be construed to limit the scope of the present invention.
FIGS. 3A to 3F are schematic cross-sectional views showing a method for fabricating a semiconductor package 3 according to a first embodiment of the present invention. The method of the present embodiment is performed on a wafer or full panel level.