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US 2016/0078969 A1Published application
Efficient coding for memory redundancy
AssigneeQUALCOMM Incorporated
InventorsChulmin Jung, Sei Seung Yoon, Robert Henry Hoem
Life of this patent
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Abstract
A system may be provided that provides redundancy for a plurality of embedded memories such as SRAMs. The system may include one or more decoders, each capable of decoding a selection address to identify a defective one of the embedded memories.
Claims20
A system, comprising:
- a plurality of embedded memories each having redundancy;
- and
- a first decoder configured to decode a first selection address into a first redundancy enable signal for a first selected one of the embedded memories.
A method, comprising:
- decoding a selection address to assert a selection signal that identifies a defective embedded memory within an array of embedded memories;
- and
- decoding a redundancy address to identify a defective feature to be replaced by a redundant feature responsive to the assertion of the selection signal.
A system, comprising:
- a plurality of embedded memories each having redundancy;
- and
- means for decoding a first selection address into a first redundancy enable signal for a first selected one of the embedded memories.
Dependencies are inferred from the claim text.