Anti-fuse type one-time programmable memory cell and anti-fuse type one-time programmable memory cell arrays
AssigneeSK hynix Inc.
InventorSung Kun PARK
Life of this patent
Estimating the term…
Abstract
An anti-fuse type OTP memory cell includes a first anti-fuse transistor having a first channel width, a first selection transistor sharing a first active region with the first anti-fuse transistor and having a second channel width that is greater than the first channel width, a second anti-fuse transistor sharing a program gate with the first anti-fuse transistor and having a third channel width, and a second selection transistor sharing a second active region with the second anti-fuse transistor and having a fourth channel width that is greater than the third channel width.
Claims13
An anti-fuse type one-time programmable (OTP) memory cell comprising:
- a first anti-fuse transistor having a first channel width;
- a first selection transistor sharing a first active region with the first anti-fuse transistor and having a second channel width that is greater than the first channel width;
- a second anti-fuse transistor sharing a program gate with the first anti-fuse transistor and having a third channel width;
- and
- a second selection transistor sharing a second active region with the second anti-fuse transistor and having a fourth channel width that is greater than the third channel width.
An anti-fuse type one-time programmable (OTP) memory cell comprising:
- a first anti-fuse transistor;
- a second anti-fuse transistor sharing a program gate with the first anti-fuse transistor;
- a first selection transistor connected in series to the first anti-fuse transistor and having a channel width that is greater than a channel width of the first anti-fuse transistor;
- and
- a second selection transistor connected in series to the second anti-fuse transistor and having a channel width that is greater than a channel width of the second anti-fuse transistor.
An anti-fuse type one-time programmable (OTP) memory cell array comprising:
- a plurality of program lines extending in one direction;
- a plurality of word lines including a first word line and a second word line respectively disposed at both sides of each of the program lines, the word lines being parallel with the program lines;
- a plurality of bit lines intersecting the word lines;
- and
- a plurality of anti-fuse type OTP memory cells respectively located at cross points of the program lines and the bit lines,
- wherein each of the anti-fuse type OTP memory cells comprises:
- a first anti-fuse transistor;
- a second anti-fuse transistor sharing any one of the program lines with the first anti-fuse transistor;
- a first selection transistor connected in series to the first anti-fuse transistor and connected to any one of the first word lines;
- and
- a second selection transistor connected in series to the second anti-fuse transistor and connected to any one of the second word lines,
- wherein the first selection transistor shares any one of the bit lines with the second selection transistor.
Dependencies are inferred from the claim text.