Non-volatile semiconductor memory device

A method of controlling a non-volatile semiconductor memory device comprising a plurality of memory cells including a first memory cell and a second memory cell stacked above the first memory cell, a plurality of word lines including first and second word lines connected to first and second memory cells, respectively, and a driver circuit connected to the word lines to supply voltages of different levels to the gates of the memory cells, said method comprising:

• supplying during a reading operation on a selected memory cell, a first voltage to other, non-selected memory cells at a first timing and a second voltage to the selected memory cell at a second timing that is after a time period after the first timing, wherein
• the time period when the first memory cell is the selected memory cell is less than the time period when the second memory cell is the selected memory cell.

A non-volatile semiconductor memory device comprising:

• a plurality of memory cells including a first memory cell and a second memory cell stacked above the first memory cell;
• a control circuit configured to apply a first voltage to a gate of the first memory cell from a first timing when the non-volatile semiconductor memory device receives a read command and a first address corresponding to the first memory cell, the control circuit being configured to apply the first voltage to a gate of the second memory cell from a second timing when the non-volatile semiconductor memory device receives a read command and a second address corresponding to the second memory cell, the first timing being different from the second timing.