Back to results
US 2016/0078956 A1Published application
Memory Device
AssigneeRenesas Electronics Corporation
InventorToshiaki Takeshita
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory cell array including a plurality of memory cells, a common source line to which sources of the plurality of memory cells are commonly connected, and a second electrical connection path further connecting the common source line to a ground voltage using erase-mode memory cells when the common source line forms a first electrical connection path and is connected to the ground voltage.
Claims15
1-18. (canceled)
A memory device, comprising:
- a sense amplifier;
- a data memory cell in which data are stored and erased;
- an erase mode memory cell in which data are only erased;
- a common source line, connected to the data memory cell and the erase mode memory cell, to provide a first electrical connection path from the data memory cell to a ground voltage;
- a word line connected to the data memory cell and the erase mode memory cell;
- a first bit line that connects the sense amplifier to the data memory cell;
- and
- a second bit line that connects the erase mode memory cell to the ground voltage,
- wherein, when a voltage is applied to the word line, the erase mode memory cell changes to an on-state to provide a second electrical connection path from the data memory cell to the ground voltage.
6 more elements
A memory device, comprising:
- a sense amplifier;
- a bit line selector connected to the sense amplifier;
- a plurality of data memory cells in which data are stored and erased;
- a plurality of erase mode memory cells in which data are only erased;
- a common source line, connected to the data memory cells and the erase mode memory cells, to provide a first electrical connection path from the data memory cells to a ground voltage;
- a plurality of word lines connected to the data memory cells and the erase mode memory cells, each word line being connected to one of the erase mode memory cells;
- a plurality of bit lines connected to the bit line selector and the data memory cells;
- and
- a ground bit line that connects the erase mode memory cells to the ground voltage,
- wherein, when a voltage is applied to one of the word lines, the erase mode memory cell connected to the word line changes to an on-state to provide a second electrical connection path from the data memory cells connected to the word line to the ground voltage,
- wherein a y-address decoder decodes a y-address signal and controls the bit line selector based on the decoded y-address signal, and
- wherein an x-address decoder decodes an x-address signal and applies a voltage to one of the plurality of word lines based on the decoded x-address signal.
9 more elements
Dependencies are inferred from the claim text.