US 2016/0078953 A1 · SEMICONDUCTOR MEMORY DEVICE

Abstract

A semiconductor memory device includes a first memory cell and a second memory cell having a parasitic capacitance smaller than a parasitic capacitance of the first memory cell, a first bit line that is electrically connected to the first memory cell, a second bit line that is electrically connected to the second memory cell, a first sense module that is electrically connected to the first bit line through a first transistor, and a second sense module that is electrically connected to the second bit line through a second transistor. During sensing of the first and second bit lines, the first and second transistors are turned on for first and second periods of time, respectively, to electrically connect the first and second sense modules to the corresponding first and second bit lines. The first period of time is longer than the second period of time.

Claims20

Dependent claims

A semiconductor memory device comprising:

a memory cell array including a first memory cell and a second memory cell having a parasitic capacitance smaller than a parasitic capacitance of the first memory cell;
a first bit line that is electrically connected to the first memory cell;
a second bit line that is electrically connected to the second memory cell;
a first sense module that is electrically connected to the first bit line through a first transistor;
and
a second sense module that is electrically connected to the second bit line through a second transistor, wherein
during sensing data stored in the first memory cell, the first transistor is turned on for a first period of time to electrically connect the first sense module to the first bit line, and
during sensing data stored in the second memory cell, the second transistor is turned on for a second period of time that is shorter than the first period of time, to electrically connect the second sense module to the second bit line.

5 more elements

A semiconductor memory device comprising:

a memory cell array including a first memory cell and a second memory cell having a parasitic capacitance smaller than a parasitic capacitance of the first memory cell;
a first bit line that is electrically connected to the first memory cell;
a second bit line that is electrically connected to the second memory cell;
a first sense module that is electrically connected to the first bit line through first and second transistors that control precharging of the first bit line;
and
a second sense module that is electrically connected to the second bit line through third and fourth transistors that control precharging of the second bit line, wherein
during precharging of the first bit line, the first and second transistors are turned on substantially at the same time, and
during precharging of the second bit line, the third transistor is turned on and the fourth transistor is turned on a period of time thereafter.

5 more elements

A semiconductor memory device comprising:

a memory cell array including a first memory cell and a second memory cell having a parasitic capacitance smaller than a parasitic capacitance of the first memory cell;
a first bit line that is electrically connected to the first memory cell;
a second bit line that is electrically connected to the second memory cell;
a first sense module that is electrically connected to the first bit line through a first transistor that controls precharging of the first bit line;
and
a second sense module that is electrically connected to the second bit line through a second transistor that controls precharging of the second bit line, wherein
during precharging of the first bit line, a first control voltage is applied to a gate of the first transistor to turn on the first transistor, and
during precharging of the second bit line, a second control voltage, lower than the first control voltage, is applied to a gate of the second transistor to turn on the second transistor.

5 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims20