Semiconductor memory device

A semiconductor memory device comprising:

• a memory cell array including a first set of memory cells commonly connected to a first word line, and a second set of memory cells commonly connected to a second word line;
• and
• a control circuit configured to execute a writing operation on the memory cells, including controlling voltages applied to the first and second word lines, wherein the writing operation includes an initial program operation, a coarse program operation and a fine program operation, and the control circuit executes the writing operation on the first and second sets of memory cells in a single write operation that includes performing the initial program operation on the first and second sets of memory cells, and then starting the following operations in order:
• (1) the coarse program operation on the first set of memory cells;
• (2) the coarse program operation on the second set of memory cells;
• (3) the fine program operation on the first set of memory cells;
• and
• (4) the fine program operation on the second set of memory cells.

A method of performing a write operation on first and second sets of memory cells of a semiconductor memory device, wherein the first set of memory cells is commonly connected to a first word line, and the second set of memory cells is commonly connected to a second word line, said method comprising:

• executing a writing operation on the first and second sets of memory cells, including controlling voltages applied to the first and second word lines, as a single write operation that includes starting the following operations in order:
• (1) the coarse program operation on the first set of memory cells;
• (2) the coarse program operation on the second set of memory cells;
• (3) the fine program operation on the first set of memory cells;
• and
• (4) the fine program operation on the second set of memory cells.