Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorMasanobu SHIRAKAWA
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a first memory string including a first memory cell and a second memory cell, a second memory string including a third memory cell, a bit line connected to both one end of the first memory string and one end of the second memory string, a first word line connected to gates of the first and third memory cells, a second word line connected to a gate of the second memory cell, and a control circuit configured to determine a program condition of the first memory cell that have been selected for a write operation, and perform the write operation for the third memory cell based on the program condition of the first memory cell.
Claims15
A semiconductor memory device comprising:
- a first memory string including a first memory cell and a second memory cell;
- a second memory string including a third memory cell;
- a bit line connected to both one end of the first memory string and one end of the second memory string;
- a first word line connected to gates of the first and third memory cells;
- a second word line connected to a gate of the second memory cell;
- and
- a control circuit configured to determine a program condition of the first memory cell that have been selected for a write operation, and perform the write operation for the third memory cell based on the program condition of the first memory cell.
A memory system comprising:
- a memory device including
- a first memory string including a first memory cell and a second memory cell,
- a second memory string including a third memory cell,
- a bit line connected to both one end of the first memory string and one end of the second memory string,
- a first word line connected to gates of the first and third memory cells,
- a second word line connected to a gate of the second memory cell, and
- a first controller configured to determine a program condition of the first memory cell when the device receives a first command and a first address before receiving a write command for the third memory cell, the first address corresponding to the first memory cell, the first controller being configured to perform the write operation for the third memory cell based on the program condition of the first memory cell;
- and
- a second controller configured to output the first command and the first address before receiving the write command for the third memory cell.
Dependencies are inferred from the claim text.