Memory system and controller
AssigneeKabushiki Kaisha Toshiba
InventorsTetsufumi YANAGIDA, Masanobu SHIRAKAWA, Toshihiro SUZUKI
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Abstract
A memory system includes a semiconductor memory device and a controller. The semiconductor memory device performs a writing operation with either a first writing method or a second writing method. The controller selects one of the first writing method and the second writing method upon receipt of a write instruction and output a write command indicating the selected writing method to the semiconductor memory device. The controller selects the writing method in accordance with a storage location in the semiconductor memory device targeted by the write instruction.
Claims19
A memory system, comprising:
- a semiconductor memory device configured to perform a writing operation with either a first writing method or a second writing method;
- and
- a controller configured to select one of the first writing method and the second writing method upon receipt of a write instruction and output a write command indicating the selected writing method to the semiconductor memory device, the selection of the writing method being made in accordance with a storage location in the semiconductor memory device targeted by the write instruction.
A controller for a semiconductor memory device configured to perform a writing operation with either a first writing method or a second writing method and a reading operation with either a first reading method or a second reading method, comprising:
- a host interface unit;
- and
- a processing unit configured to select one of the first writing method and the second writing method upon receipt of a write instruction received through host interface unit and output a write command indicating the selected writing method to the semiconductor memory device, the selection of the writing method being made in accordance with a storage location in the semiconductor memory device targeted by the write instruction.
A memory system comprising:
- a semiconductor memory device including a plurality of memory cell transistors, the semiconductor memory device being configured to perform a writing operation with either a first writing method or a second writing method, the semiconductor memory device being configured to apply a first positive voltage to a gate of a selected memory cell in the first writing method, the semiconductor memory device being configured to apply a first negative voltage to the gate of the selected memory cell in the second writing method;
- and
- a controller configured to select one of the first writing method and the second writing method upon receipt of a write instruction and output a write command indicating the selected writing method to the semiconductor memory device.
Dependencies are inferred from the claim text.