Resistive memory device and control method thereof

A resistive memory device, comprising:

• a first cell coupled to a word line, a first bit line and a source line;
• a second cell coupled to the word line, a second bit line and the source line;
• and
• a control circuit controlling levels of the word line, the first bit line and the source line to execute a set operation for the first cell such that the first cell has a first resistance, and controlling levels of the word line, the second bit line and the source line to execute a reset operation for the second cell such that the second cell has a second resistance greater than the first resistance,
• wherein during the execution of the set operation, the control circuit asserts the level of the source line at a pre-determined level and during the execution of the reset operation, the control circuit asserts the level of the source line at the pre-determined level,
• wherein the pre-determined level is a ground level and the control circuit simultaneously executes the set and reset operations.