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US 2016/0078934 A1Published application
1t-1r architecture for resistive random access memory
AssigneeRambus Inc.
InventorsDeepak Chandra Sekar, Wayne Frederick Ellis
Life of this patent
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Abstract
A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled in series to a first resistive memory element and a second switching element electrically coupled in series to a second resistive memory element. A source of the first switching element and a source of the second switching element receive a common source line signal.
Claims20
A method of operating an array of memory cells, comprising:
- applying a selected source line voltage to a selected source line corresponding to a selected memory cell that is selected for an operation;
- applying an unselected source line voltage that is different from the selected source line voltage to unselected source lines corresponding to unselected memory cells that are not selected for the operation;
- applying a selected word line voltage to a selected word line corresponding to the selected memory cell;
- and
- forming or setting the selected memory cell in response to applying the selected word line voltage to the selected word line;
- wherein each memory cell includes a resistive memory element electrically coupled in series to a corresponding transistor having a gate coupled to receive a corresponding one of a plurality of word lines and a source coupled to receive a corresponding one of a plurality of source lines.
3 more elements
A method of operating an array of resistive memory cells, comprising:
- applying a selected source line voltage to a selected source line corresponding to a selected memory cell that is selected for an operation;
- applying an unselected source line voltage that is different from the selected source line voltage to unselected source lines corresponding to unselected memory cells that are not selected for the operation;
- applying a selected word line voltage to a selected word line corresponding to the selected memory cell;
- and
- performing the operation on the selected memory cell;
- wherein the array of resistive memory cells is coupled to receive a plurality of word lines, a plurality of source lines, and a plurality of bit lines;
- and
- wherein each pair of resistive memory cells includes a first resistive memory element, a second resistive memory element, a first switching element electrically coupled in series to the first resistive memory element and having a first gate coupled to receive a first word line of the plurality of word lines and a first source coupled to receive a first source line of the plurality of source lines, and a second switching element electrically coupled in series to the second resistive memory element and having a second gate to receive a second word line of the plurality of word lines and a second source electrically coupled to the first source to receive the first source line of the plurality of source lines.
5 more elements
A memory device, comprising:
- a plurality of word lines;
- a plurality of source lines;
- and
- an array of resistive memory cells including pairs of resistive memory cells, each pair of resistive memory cells including:
- a first resistive memory element;
- a second resistive memory element;
- a first switching element electrically coupled in series to the first resistive memory element and having a first gate coupled to receive a first word line of the plurality of word lines and a first source coupled to receive a first source line of the plurality of source lines;
- and
- a second switching element electrically coupled in series to the second resistive memory element and having a second gate coupled to receive a second word line of the plurality of word lines and a second source electrically coupled to the first source to receive the first source line of the plurality of source lines.
6 more elements
Dependencies are inferred from the claim text.