US 2016/0078932 A1Published application

Semiconductor storage device

AssigneeHitachi, Ltd.

InventorsYoshitaka SASAGO, Hiroyuki MINEMURA, Kenzo KUROTSUCHI, Seiji MIURA, Satoru HANZAWA

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Abstract

An object of this invention is to provide a semiconductor memory device capable of increasing the read transfer rate by performing the read operation in parallel while suppressing the voltage drop when a large current is passed to a memory chain and reducing a chip area by reducing the number of peripheral circuits to feed power. A semiconductor memory device according to this invention includes upper and lower electrodes in a flat plate shape, first and second select transistors extending in first and second directions respectively, and a wire arranged between the first select transistor and the second select transistor and the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor (see FIG. 2).

Claims15

Dependent claims

A semiconductor memory device, comprising:

a lower electrode in a flat plate shape and an upper electrode in the flat plate shape;
a plurality of first select transistors arranged between the lower electrode and the upper electrode, extending in a first direction, and provided along a second direction different from the first direction;
a plurality of wires connected to the lower electrode via the first select transistor and provided as a pair of each of the first select transistors;
a plurality of second select transistors arranged between the wire and the upper electrode, extending in the second direction, and provided along the first direction;
and
a plurality of memory chains having one or more memory cells connected in series in a normal direction to the lower electrode and the upper electrode, each memory chain provided along the first direction and the second direction, wherein
the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor.

4 more elements

A semiconductor memory device, comprising:

a plurality of memory chains having one or more memory cells connected in series in a normal direction to a substrate and provided along a first direction and a second direction parallel to the substrate;
a first selector that selects one of the memory chains in the first direction;
a second selector that selects one of the memory chains in the second direction;
and
a control circuit that controls the first selector and the second selector to program the information into the memory cell or to read the information from the memory cell, wherein
the memory cell is formed by connecting in parallel a cell transistor and a phase change element and
when the one or more memory chains adjacent along the first direction and the one or more memory chains adjacent along the second direction are selected and bulk erasing of information stored in all the selected memory chains is performed,
the control circuit
supplies a smaller current to the memory chain arranged in a center portion of a region containing each of the selected memory chains than a current to the memory chain arranged in a peripheral portion of the center portion and also makes a time of supplying the current shorter so that Joule heat generated by the current on the phase change element is smaller in the center portion than in the peripheral portion.

6 more elements

Dependencies are inferred from the claim text.