Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorHiroshi MAEJIMA
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Abstract
A semiconductor memory device includes a memory cell, a bit line electrically connected to a first end of the memory cell, a source line electrically connected to a second end of the memory cell, a sense amplifier electrically connected to the bit line, and a controller configured to perform a read operation including first and second read operations on the memory cell. During the first read operation, a pre-charge voltage is applied to the bit line and a source line voltage lower than the pre-charge voltage is applied to the source line, and during the second read operation, a first voltage that is greater than the source line voltage and less than the pre-charge voltage is applied to the bit line.
Claims20
A semiconductor memory device comprising:
- a memory cell;
- a bit line electrically connected to a first end of the memory cell;
- a source line electrically connected to a second end of the memory cell;
- a sense amplifier electrically connected to the bit line;
- and
- a controller configured to perform a read operation including first and second read operations on the memory cell, wherein, during the first read operation, a pre-charge voltage is applied to the bit line and a source line voltage lower than the pre-charge voltage is applied to the source line, and during the second read operation, a first voltage that is greater than the source line voltage and less than the pre-charge voltage is applied to the bit line.
A method of performing a read operation including first and second read operations in a semiconductor memory device having a memory cell, a bit line electrically connected to a first end of the memory cell, a source line electrically connected to a second end of the memory cell, and a sense amplifier electrically connected to the bit line, said method comprising:
- during the first read operation, applying a pre-charge voltage to the bit line and a source line voltage lower than the pre-charge voltage to the source line;
- and
- during the second read operation, applying a first voltage that is greater than the source line voltage and less than the pre-charge voltage to the bit line.
A semiconductor memory device comprising:
- first and second memory cells, each configured to store two or more bits;
- a first bit line electrically connected to a first end of the first memory cell;
- a second bit line electrically connected to a first end of the second memory cell;
- a source line electrically connected to second ends of the first and second memory cells;
- a sense amplifier electrically connected to the first and second bit lines;
- and
- a controller configured to perform a read operation including first, second, third, and fourth read operations on the memory cell, to distinguish among at least four threshold voltage levels of the first and second memory cells, wherein
- during the first read operation, a pre-charge voltage is applied to the first and second bit lines and a source line voltage lower than the pre-charge voltage is applied to the source line,
- during the second read operation, the pre-charge voltage is applied to the first bit line and a first voltage that is greater than the source line voltage and less than the pre-charge voltage is applied to the second bit line,
- during the third read operation, the pre-charge voltage is applied to the first bit line, and
- during the fourth read operation, the first voltage is applied to the first bit line.
Dependencies are inferred from the claim text.