Nand array hiarchical bl structures for multiple-wl and all-bl simultaneous erase, erase-verify, program, program-verify, and read operations

A high-density NAND (HiNAND) flash memory array with 2-level broken-bit-line hierarchical architecture for performing multiple-WL All-BL simultaneous Program, Program-Verify, and Read operations, the HiNAND flash memory array comprising:

• a NAND memory array arranged in a first plurality of Groups per N columns respectively associated with N global bit lines (GBLs) laid in parallel at a first level through all Groups and N local bit lines (LBLs) laid at a second level below the first level parallel to the GBLs through only a Segment of each Group, the N GBLs being respectively divided into the first plurality of N broken-GBLs separated/connected from/to each other correspondingly by a row of N Group-divided devices, each Group comprising a second plurality of Segments with each Segment being divided into a third plurality of Sub-segments such that the N LBLs per Segment are respectively divided into the third plurality of N broken-LBLs separated/connected from/to each other correspondingly by a row of N Segment-divided devices, each Sub-segment including multiple Blocks, each Block including M Pages of NAND memory cells forming into N Strings, each String having M NAND memory cells connected in series capped by a first String-select device coupled to a broken-LBL associated with the Sub-segment and a second String-select device coupled to a common source line in parallel to a word line (WL) of each Page;
• a row of N Segment-select devices respectively coupled the N broken-GBLs per Group at the first level to the N LBLs per Segment in the Group at the second level;
• a row of N precharge pull-down devices respectively coupled the N broken-LBLs per Sub-segment to a precharge-power line laid at a third level below the second level for precharging and discharging all the N broken-LBLs in the Sub-segment selected from any Segment of any Group independent from other Segments in all Groups;
• and
• a page buffer having N-bit ports to couple with the N GBLs, the page buffer comprising at least a first Data Register coupled with a first Cache Register located a first one of the first plurality of Groups;
• wherein each row of N GBL-divided devices is gated by one of first control signals, each row of N Segment-divided devices is gated by one of second control signals, each row of N Segment-select devices is controlled by one of third control signals, each row of N precharge pull-down devices is controlled by one of fourth control signals, multiple Pages with respective multiple WLs and all GBLs across the array can be selected on one-page-per-block basis from multiple dispersed Blocks in multiple different Sub-segments of one or more Segments of one or more Groups for at least partially performing simultaneous Program, Program-Verify, and Read operations.