Design-for-test apparatuses and techniques

A method of operating a design-for-test (DFT) device, comprising:

• providing the DFT device, the DFT device comprising:
• a static random access memory (SRAM) cell comprising a word line (WL) to receive an applied WL voltage and a bit line (BL) to receive an applied BL voltage,
• read/write/decoder circuitry to selectively provide first and second WL voltages for application to the WL during accesses, and selectively provide first and second BL voltages for application to the BL during accesses, wherein the first WL voltage is greater than the second WL voltage and the first BL voltage is greater than the second BL voltage, and
• test circuitry, coupled to the SRAM cell and the read/write/decoder circuitry, having an activated state and a deactivated state;
• causing the test circuitry to enter the activated state, in which:
• when the read/write/decoder circuitry provides the first WL voltage, the applied WL voltage is less than the first WL voltage, or
• when the read/write/decoder circuitry provides the second BL voltage, the applied BL voltage is greater than the second BL voltage;
• operating the read/write/decoder circuitry to perform accesses to the SRAM cell while the test circuitry is in the activated state.

A method of stimulating operation of a static random access memory (SRAM) cell under pre-determined temperature conditions, comprising:

• providing a design-for-test apparatus, the DFT apparatus comprising:
• the SRAM cell, comprising a word line (WL) to receive an applied WL voltage and a bit line (BL) to receive an applied BL voltage,
• read/write/decoder circuitry to selectively provide first and second WL voltages for application to the WL during accesses, and selectively provide first and second BL voltages for application to the BL during accesses,
• power supply circuitry to provide a supply voltage, and
• test circuitry, coupled to the SRAM cell and the read/write/decoder circuitry and the power supply circuitry, having first and second activated states and a deactivated state;
• causing the test circuitry to enter the first or second activated state, wherein:
• in the first activated state, when the read/write/decoder circuitry provides the first WL voltage, the applied WL voltage is less than the first WL voltage and the applied array line voltage is less than the supply voltage,
• in the second activated state, (1) when the read/write/decoder circuitry provides the first WL voltage, the applied WL voltage is less than the first WL voltage and the applied array line voltage is the supply voltage, or (2) when the read/write/decoder circuitry provides the second BL voltage, the applied BL voltage is greater than the second BL voltage;
• operating the read/write/decoder circuitry to perform accesses to the SRAM cell while the test circuitry is in the first or second activated states, wherein:
• while the test circuitry is in the first activated state, operating the read/write/decoder circuitry simulates operation of the SRAM cell under temperature conditions greater than room temperature, and
• while the test circuitry is in the second and state, operating the read/write/decoder circuitry simulates operation of the SRAM cell under temperature conditions less than room temperature.