Dual-port static random access memory (sram)
AssigneeIntel Corporation
InventorsPramod Kolar, Gunjan H. Pandya, Uddalak Bhattacharya, Zheng Guo
Life of this patent
Estimating the term…
Abstract
In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.
Claims22
A memory cell circuit for storing data, comprising:
- a plurality of p-type metal oxide semiconductor (PMOS) devices and a plurality of n-type metal oxide semiconductor (NMOS) devices for storing states of the memory cell circuit;
- a plurality of access devices with each access device being coupled to at least one of the plurality of PMOS devices and at least one of the plurality of NMOS devices, the plurality of access devices to provide access for storing states of the memory cell circuit;
- and
- a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices coupled to the plurality of PMOS devices, the set of electrically inactive PMOS devices in combination with the plurality of PMOS devices to enable a continuous p-type diffusion layer for the memory cell circuit.
An apparatus for storing data, comprising:
- means for storing states of the apparatus with electrically active p-type metal oxide semiconductor (PMOS) devices and n-type metal oxide semiconductor (NMOS) devices;
- means for providing access for storing states of the apparatus;
- and
- a set of electrically inactive PMOS devices coupled to the electrically active PMOS devices, the set of electrical inactive PMOS devices in combination with the electrically active PMOS devices to enable a continuous p-type diffusion layer for the PMOS devices of the apparatus.
A computing device, comprising:
- a processor;
- a communication chip coupled to the processor;
- and
- one or more arrays each including a plurality of memory cell circuits, each memory cell circuit comprising,
- a plurality of p-type metal oxide semiconductor (PMOS) devices and a plurality of n-type metal oxide semiconductor (NMOS) devices for storing states of the memory cell circuit;
- a plurality of access devices with each access device being coupled to at least one of the plurality of PMOS devices and at least one of the plurality of NMOS devices, the plurality of access devices to provide access for storing states of the memory cell circuit;
- and
- a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices coupled to the plurality of PMOS devices, the set of electrically inactive PMOS devices in combination with the plurality of PMOS devices to enable a continuous p-type diffusion layer for the memory cell circuit.
Dependencies are inferred from the claim text.