Semiconductor memory device that can stably perform writing and reading without increasing current consumption even with a low power supply voltage

A semiconductor device comprising:

• a power supply node for a power supply voltage;
• a pair of bit lines;
• a plurality of word lines;
• a plurality of memory cells coupled to the pair of bit lines and the plurality of word lines so that one memory cell is coupled to one word line and the pair of bit lines;
• a cell power supply line coupled to the plurality of memory cells;
• a pair of data lines (IO);
• a column select gate coupled to receive a column select signal and for coupling the pair of bit lines to the pair of data lines, respectively, based on the column select signal;
• and
• a p-channel type MOS transistor coupled to receive the column select signal and for coupling the power supply node to the cell power supply line based on the column select signal,
• wherein, among the plurality of memory cells, a memory cell coupled closest to the p-channel type MOS transistor via the cell power supply line is coupled closest to the column select gate via the pair of bit lines.

A semiconductor device comprising:

• a power supply node for a power supply voltage;
• a pair of bit lines;
• a plurality of word lines;
• a plurality of memory cells coupled to the pair of bit lines and the plurality of word lines so that one memory cell is coupled to one word line and the pair of bit lines;
• a cell power supply line coupled to the plurality of memory cells;
• a pair of data lines;
• a column select gate which is coupled to receive a column select signal and which couples the pair of bit lines to the pair of data lines, respectively, based on the column select signal;
• and
• a p-channel type MOS transistor which couples the power supply node to the cell power supply line based on the column select signal and a write instruction signal,
• wherein, among the plurality of memory cells, a memory cell coupled closest to the p-channel type MOS transistor via the cell power supply line is coupled closest to the column select gate via the pair of bit lines, and
• wherein the p-channel type MOS transistor disconnects the power supply node to the cell power supply line based on the active of the column select signal and the active of the write instruction signal.

A semiconductor device comprising:

• a power supply node for a power supply voltage;
• a pair of bit lines;
• a plurality of word lines;
• a plurality of memory cells coupled to the pair of bit lines and the plurality of word lines so that one memory cell is coupled to one word line and the pair of bit lines, each of the plurality of memory cells including:
• a first inverter having an input coupled to a first storage node and an output coupled to a second storage node,
• a second inverter having an input coupled to the second storage node and an output coupled to the first storage node,
• a first access transistor having a gate coupled to one of the plurality of word lines and a source-drain path coupled between one of the pair of bit lines and the first storage node;
• and
• a second access transistor having a gate coupled to the one of the plurality of word lines and a source-drain path coupled between the other of the pair of bit lines and the second storage node;
• a cell power supply line coupled to the plurality of memory cells;
• a pair of data lines;
• a column select gate which is coupled to receive a column select signal and which couples the pair of bit lines to the pair of data lines, respectively, based on the column select signal;
• and
• a p-channel type MOS transistor which couples the power supply node to the cell power supply line based on the column select signal and a write instruction signal,
• wherein, among the plurality of memory cells, a memory cell coupled closest to the p-channel type MOS transistor via the cell power supply line is coupled closest to the column select gate via the pair of bit lines, wherein the p-channel type MOS transistor disconnects the power supply node to the cell power supply line based on the active of the column select signal and the active of the write instruction signal.