Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorTsuyoshi MIDORIKAWA
Life of this patent
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Abstract
In an embodiment, a semiconductor memory device includes a memory cell that includes a first inverter having a first input and a first output, and a second inverter having a second input connected to the first output and a second output connected to first input portion. A first bit line that is connected to the first output of the first inverter via a first transmission transistor. A second bit line is connected to the second output of the second inverter via a second transmission transistor. A first p channel MOS transistor has a drain connected to the first bit line, and a gate connected to the second bit line. A second p channel MOS transistor has a drain connected to the second bit line and a gate connected to the first bit line.
Claims20
A semiconductor memory device, comprising:
- a memory cell including:
- a first inverter having a first input and a first output, and
- a second inverter having a second input connected to the first output and a second output connected to the first input;
- a first bit line connected to the first output via a first transmission transistor;
- a second bit line connected to the second output via a second transmission transistor;
- a first p channel metal-oxide-semiconductor (MOS) transistor having a drain connected to the first bit line and a gate connected to the second bit line;
- and
- a second p channel MOS transistor having a drain connected to the second bit line and a gate connected to the first bit line.
A semiconductor memory device, comprising:
- a first memory cell including:
- a first inverter having a first input and a first output, and
- a second inverter having a second input connected to the first output and a second output connected to the first input;
- a first bit line connected to the first output via a first transmission transistor;
- a second bit line connected to the second output via a second transmission transistor;
- a second memory cell including:
- a third inverter having a third input and a third output, and
- a fourth inverter having a fourth input connected to the third output and a fourth output connected to third input, the fourth output connected to a power supply voltage;
- a third bit line connected to the third output via a third transmission transistor;
- a delay circuit configured to delay a signal voltage supplied on the third bit line and having an delay signal output at which the signal voltage is output as a delayed signal voltage after a predetermined delay period;
- a fifth inverter having an input connected to the second bit line;
- a first p channel metal-oxide-semiconductor (MOS) transistor having a gate connected to the delay signal output and a source connected to the power supply voltage;
- and
- a second p channel MOS transistor having a source connected to a drain of the first p channel MOS transistor, a drain connected to the second bit line, and a gate connected to an output of the fifth inverter.
A memory device, comprising:
- a first static-random access memory (SRAM) cell connected to a word line and a complementary pair of bit lines;
- a precharging circuit configured to charge the complementary pair of bit lines to a first voltage level in response to a precharging signal;
- and
- a reading circuit connected to a first bit line in the complementary pair of bit lines and configured to connect the first bit line to a power supply voltage when the first bit line has a first bit line voltage level that is equal to or greater than the first voltage level and to disconnect the first bit line from the power supply voltage when the first bit line has the first bit line voltage level that is less than the first voltage level.
Dependencies are inferred from the claim text.