Semiconductor memory device compensating difference of bitline interconnection resistance

A semiconductor memory device, comprising:

• a memory cell array having a plurality of memory cells, each of the memory cells including one access transistor and one storage capacitor;
• a cross-coupled type bit line sense amplifier to sense an electric potential difference of a bit line pair during a sensing operation for reading data stored in at least one memory cell of the plurality of memory cells;
• and
• first and second column select gates connected to the bit line sense amplifier to transfer an electric potential on the bit line pair to a local sense amplifier, wherein the first and second column select gates have different sizes from each other to compensate a difference in bit line interconnection length.

A circuit, comprising:

• a first column select gate to transfer an electric potential on a first bit line to a sense amplifier based on a column select signal;
• and
• a second column select gate to transfer an electric potential on a second bit line to the sense amplifier based on the column select signal, the first and second bit lines being complementary bit lines, wherein:
• the first bit line is separated from the first column select gate by a first interconnection length,
• the second bit line is separated from the second column select gate by a second interconnection length, and
• the first and second column select gates have different current drive abilities based on a difference between the first and second interconnection lengths.