US 2016/0078918 A1 · MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME

Abstract

A memory device includes: a plurality of memory blocks; an address counting block suitable for generating a counting address that is changed when all the memory blocks are refreshed; a target address generation block suitable for generating a target address, which is an address of a word line requiring an additional refresh operation, in the memory blocks; and a refresh control block suitable for controlling a 1st number of the memory blocks to be refreshed to when a refresh command is inputted a 1st number of times and controlling a 2nd number of the memory blocks to be refreshed when the refresh command is inputted a 2nd number of times, wherein the refresh control block controls a word line corresponding to the counting address to be refreshed and controls a word line corresponding to the target address to be refreshed during a target refresh operation.

Claims25

Dependent claims

A memory device, comprising:

a plurality of memory blocks;
an address counting block suitable for generating a counting address that is changed when all the memory blocks are refreshed;
a target address generation block suitable for generating a target address, which is an address of a word line requiring an additional refresh operation in the memory blocks;
and
a refresh control block suitable for controlling a 1st number of the memory blocks to be refreshed when a refresh command is inputted a 1st number of times and controlling a 2nd number of the memory blocks to be refreshed when the refresh command is inputted a 2nd number of times,
wherein the refresh control block controls a word line corresponding to the counting address to be refreshed, and when a target refresh operation is performed, controls a word line corresponding to the target address to be refreshed.

3 more elements

A memory device, comprising:

a plurality of memory blocks;
a mode setting block suitable for setting a 1st mode or a 2nd mode for refreshing a 1st number of the memory blocks or a 2nd number of the memory blocks, which is smaller than the 1st number of the memory blocks, respectively, at one time under control of a memory controller;
and
a refresh control block suitable for controlling the 1st number of the memory blocks to be refreshed when a refresh command is inputted while the 2nd mode is set by the mode setting block,
wherein the refresh control block controls a word line corresponding to a counting address, which is changed when the memory blocks are refreshed, to be refreshed and controls a word line corresponding to a target address, which is an address of a word line requiring an additional refresh operation, to be refreshed during a target refresh operation.

2 more elements

A memory system, comprising:

a memory device including a plurality of memory blocks, wherein the memory device is set to a 1st mode or a 2nd mode for refreshing a 1st number of the memory blocks or a 2nd number of the memory blocks, which is smaller than the 1st number of the memory blocks, respectively, at one time based on inputted setting information and refreshes the 1st number of the memory blocks when a refresh command is inputted while the 2nd mode is set, and refreshes a word line corresponding to a counting address, which is changed when the memory blocks are refreshed, and a word line corresponding to a target address, which is an address of a word line requiring an additional refresh operation, during a target refresh operation;
and
a memory controller that inputs the setting information to the memory device and inputs the refresh command at a 1st period when the memory device is set to the 1st mode and inputs the refresh command at a 2nd period, which is shorter than the 1st period, when the memory device is set to the 2nd mode.

Dependencies are inferred from the claim text.

Memory device and memory system including the same

Life of this patent

Memory device and memory system including the same

Life of this patent

Abstract

Claims25