Semiconductor memory device having count value control circuit

A semiconductor device comprising:

• a plurality of data storing cells configured to store a first count value;
• and
• a count value control circuit including a register circuit configured to update the first count value to the second count value responsive to a first control signal and the count value control circuit further including a write circuit coupled between the data storing cells and the register circuit;
• the write circuit being configured to write the second count value to the data storing cells responsive to a second control signal and to write a third count value different from each of the first and second count values responsive to a third control signal.

A semiconductor device comprising:

• a memory cell array including a plurality of memory cells that are arranged in a matrix including a plurality of rows and columns, each of the rows being assigned to an individual address of row addresses;
• an access circuit configured to access each of the rows responsive to an associated individual address of the row addresses;
• and
• a plurality of counting circuits each provided for an associated one of the rows, each of the counting circuits being configured to count a number of accesses that are performed on an associated one of the rows by the access circuit, each of the counting circuits being further configured to be loaded with a first value that is free from the number of accesses.