Display and display control circuit

An image processor configured to compress image data and output compressed image data, the image processor comprising:

• a first compression circuit configured to generate compressed current data based on image data of a current frame,
• a second compression circuit configured to generate compressed previous data based on image data of a previous frame,
• a first decompression circuit configured to generate decompressed current data based on the compressed current data;
• a second decompression circuit configured to generate decompressed previous data based on the compressed previous data;
• an overdrive processing part configured to generate overdriven data based on the decompressed current data and the decompressed previous data;
• a correction circuit configured to generate corrected overdriven data by correcting the overdriven data;
• a third compression circuit configured to generate compressed corrected overdriven data based on the corrected overdriven data;
• and
• a third decompression circuit configured to generate redecompressed corrected data based on the compressed corrected data;
• a transmission circuit configured to transmit the compressed corrected data according to a comparison result of the current decompressed data and redecompressed corrected data.