Display device
AssigneeLG Display Co., Ltd.
InventorsSeungjin YOO, Wookyu SANG, Ooksang YOO
Life of this patent
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Abstract
A display device includes a pixel array having a plurality of pixels arranged in a matrix form based on a crossing structure of data lines and gate lines, a data driver having a plurality of output channels and configured to output a data voltage, a multiplexer configured to distribute the data voltage output from the data driver to the data lines in response to first and second control signals, and a gate driver configured to output a gate pulse synchronized with the data voltage in a non-sequential manner. The first and second control signals are in antiphase, and a switching cycle of the first and second control signals is one horizontal period or two horizontal periods.
Claims8
A display device comprising:
- a pixel array including a plurality of pixels arranged in a matrix form based on a crossing structure of data lines and gate lines;
- a data driver including a plurality of output channels to output a data voltage;
- a multiplexer connected between the pixel array and the data driver, and configured to distribute the data voltage output from the data driver to the data lines in response to first and second control signals from a controller;
- and
- a gate driver connected to the pixel array, and configured to output a gate pulse synchronized with the data voltage in a non-sequential manner,
- wherein the first and second control signals are in antiphase with each other, and a switching cycle of the first and second control signals is one horizontal period or two horizontal periods, and
- wherein a data switching cycle of the data voltage supplied to the pixel array is N horizontal periods, where N is a positive integer between 4 and 8.
A display device comprising:
- a pixel array including a plurality of pixels arranged in a matrix form based on a crossing structure of data lines and gate lines;
- a data driver including a plurality of output channels and configured to output a data voltage to the data lines through the plurality of output channels;
- and
- a gate driver configured to output a gate pulse synchronized with the data voltage in a non-sequential manner,
- wherein a data switching cycle of the data voltage supplied to the pixel array is N horizontal periods, where N is a positive integer between 4 and 8.
Dependencies are inferred from the claim text.